4004 Processor Data by: Mark Ormston (aka Zolaerla or MeMSO) of NeueTECH Software memso@memso.net Version: 0.1 Last Modified: 2007-01-06 [INCOMPLETE] Please leave this notice in any version of this text file! This document was made for readability in any general ASCII system, with 100 or more characters per line and 2 spaces per tab. I shall endeavor to convert all tabs to spaces before releasing a version of this document, but if I forget, this at least tells you how to correct it. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! NOTICE! Though I attempt to be as accurate as possible, I am limited to what other sources state. Often times these sources disagree with one another and I end up having to pick and choose what sounds "right", even if it may not necessarily be so. I can give no guarantee of any sort that this information is 100% accurate. I just would like to think it is! If there is any information that would make this more complete, please email me above and let me know! Please put "For MeMSO" (capitalize it properly please) in the subject so I know it's not spam (I get up to 100 of those a day!). !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! This document describes in full detail exactly how the 4004 processors work. This information was gathered so I could program the CPU cores into my emulator. Anybody that knows much of anything about emulators knows that they need to be very exact to properly emulate the systems they are designed for, and it is this exactness I sought when creating this document. Many sources were used, and I have listed as many as I could in an appendix. A .xls file should come with this file. It contains charts of the opcodes/mnemonics in Opcode and Mnemonic sort order, for reference purposes. I have used this chart extensively myself. This document currently covers the following processors: None yet What this document *IS*: o Quite Unabridged o A gathering of information from many, many different sources to consolodate information in just a couple files o Useful for details on the inner workings of these CPUs o A place to find psuedo-code for EVERY opcode (often times not optimized for clarity's sake) o Will give all information necessary to both program and to emulate these processors o System independent. The code and descriptions of the CPUs ignore any hardware they are designed for as much as is humanly possible. What this document *IS NOT*: o A teaching guide for using/programming these processors o A guide for creating computers/systems using these processors (unless you just want the CPU details) o System dependent Hexidecimal values on the 4004 processors is done with an H at the end of the value. 10H is 10 hex (16 decimal), for example. Because these processors use this convention, I am using it throughout the documentation. I personally would prefer to use 0xABCD like C/C++ does, but any other 4004 documentation will also use the ABCDH notation. Some documentation, such as [2], lists values in octal. Octal is 3bit and this processor is 4bit, so to me it makes far more sense to use 4bit hex instead! Also, most low-level programmers such as myself are far more familiar with hex as it is, and thus it will make it easier to read. Throughout this document, I may add an indented section with "* Opinion" to show when I am stating my opinion on something. These may be ignored completely but may point out something that you may not otherwise think about. ??? - I put this anywhere where I am making a guess but do not know for certain. These are very frustrating for everyone, to be sure. KERBLUH - This is what I use to tell me that more information is needed. *************************************************************************************************** TABLE OF CONTENTS 1 Description of the 4004 line of processors 2 List of processor registers 2.1 A: Adder (Accumulator) 2.2 R0-RF: Index Registers 2.3 PC: Program Counter 2.4 S: Stack Address 2.5 FF or CY: Flipflip (Carry Flag) 2.6 OPR, OPA: Instruction Registers 3 Addressing Modes 4 Opcodes 5 Pins [INCOMPLETE] 6 Quirks and Nuances [INCOMPLETE] A1 Miscellaneous Notes and Issues A2 TO DO List A3 Updates List Sources Information Sources *************************************************************************************************** 1 Description of the 4004 line of processors The 4004 is the first microprocessor created by Intel in 1971 and was essentially the first microprocessor available to the public (other companies were working on microprocessors at around the same time). It was rather unsuccessful on the market but helped to pave the way for future microprocessors, especially Intel's own 8080 series, decendents of which still live on in the Z80 line of processors. Unlike later NMOS and CMOS chips, the 4004 was made with a PMOS system (P-channel Silicon Gate MOS). The specs from [1] for the MCS-4, the computer the 4004 came with are: o Microprogrammable General Purpose Computer Set o 4-Bit Parallel CPU with 45 Instructions o Instruction Set Includes Conditional Branching, Jump to Subroutine and Indirect Fetching o Binary and Decimal Arithmetic Modes o Addition of two 8-Digit Numbers in 850 Microseconds o 2-Phase Dynamic Operation o 10.8 Microsecond [~92.6kHz] Instruction cycle o CPU Directly Compatible with RCS-4 ROMs and RAMs o Easy Expansion - One CPU can directly drive up to 32,768 Bits [4KB] of ROM and up to 5120 Bits [640 bytes] of RAM o Unlimited Number of Output Lines with 4003, 128 I/O lines without o Packed In 16-Pin Dual In-Line Configuration o Memory capacity expandable through bank switching o Sixteen 4-bit general purpose registers o Nesting of subroutines up to 3 levels o Runs at 750kHz ([3] states it ran at 740kHz) RAM is separate from ROM. Execution of the program can only occur in ROM. 4004 Considered by many to be the original micro-processor 4008 An expansion for the 4004 Added new instruction: WPM 4040 An updated 4004 introduced around 1974 that added bank switching for ROM, permitting up to 8KB of ROM, double the stack size, added an extra bank of 8 4bit registers and included interrupt support. (from [5]) [KERBLUH - NEED MORE INFORMATION] *************************************************************************************************** 2 List of processor registers ___________________________________________________________________________________________________ 2.1 A or ACC: Accumulator 4-bit. This register was used for arithmetic operations on the processor. ___________________________________________________________________________________________________ 2.2 R0-RF: Index Registers 16x4bit. The index registers could be used as 16 separate 4bit registers, or has 8 8bit registers. [4] calls these R0 to RF and since I can find no better names for them ([2] shows them in octal), this is how they will be shown in this document. When the registers are used as 8 8bit registers, the first register holds the upper nibble (values of 00 to F0) and the second register holds the lower nibble (values of 00 to 0F). ___________________________________________________________________________________________________ 2.3 PC: Program Counter 4x12bit. The program counter controls where the current code is executing. There are four "separate" values to support subroutines up to three levels deep. The stack address chooses which of the four program counters is in use at a time. ___________________________________________________________________________________________________ 2.4 S: Stack Address 2bit. This was used internally to store which of the program counters is currently in use. When a JMS (JuMp to Subroutine) is used, the stack address then points to the next program counter. When a BBL (Branch Back and Load a) is used, the stack address points to the previous program counter. If JMS or BBL is used too much, this wraps around. ___________________________________________________________________________________________________ 2.5 FF or CY: Flipflip (Carry Flag) 1bit. This is essentially a carry flag, as exists on all subsequent processors. It is used for multi-nibble math as well as condition tests. ___________________________________________________________________________________________________ 2.6 X0 to X3: RAM Address Registers 4bit each. These "registers" govern the effective address in RAM -OR- designate a ROM for an I/O port operation. ??????? ___________________________________________________________________________________________________ 2.7 OPR, OPA: Instruction Registers 4bit each. Normally not considered registers on their own in later CPU architectures, these are used to decode instruction information. OPR generally holds the upper four bits of an opcode, which contains the type of operation (OPR means OPeRation). OPA generally holds the lower four bits of an opcode, which contains the modification, register, 4bits of data or an address (OPA means OPeration Address???). *************************************************************************************************** 3 Addressing Modes ___________________________________________________________________________________________________ 3.1 Accumulator The effective address is the A (Accumulator) register. ___________________________________________________________________________________________________ 3.2 4bit Register The effective address is one of the sixteen 4bit registers. This is always stored as the lower nibble of an opcode, bits 0 - 3, which refers to the 4bit register affected. ___________________________________________________________________________________________________ 3.3 Combined Registers The effective address is two of the 4bit registers for a total 8bit value. This is always stored in the lower nibble of an opcode as bits 1 - 3 (bit 0 of the register selection is always cleared), which refers to the first of the pair of registers affected. The first register, always an even number, is the higher nibble of the 8bit value and the second register, one higher than the first, is the lower nibble of the 8bit value. ___________________________________________________________________________________________________ 3.4 Register indirect ___________________________________________________________________________________________________ 3.5 Immediate ___________________________________________________________________________________________________ 3.6 8bit Address ___________________________________________________________________________________________________ 3.7 12bit Address ___________________________________________________________________________________________________ 3.8 Memory *************************************************************************************************** 4 Opcodes ___________________________________________________________________________________________________ 4.1 How Opcodes are Built Opcodes were read in from ROM 4 bits at a time. The upper 4 bits of an opcode are always unique and always determine the opcode. The lower 4 bits of an opcode can determine the opcode (for 0x, Ex and Fx opcodes), hold three bits of register data for combined general purpose registers and a bit for determining the opcode (2x and 3x opcodes), or hold 4 bits of data to determine which general purpose register to use (6x, 7x, 8x, 9x and Ax opcodes), a 4bit immediate (Cx and Dx opcodes), or the upper 4 bits of a 12bit address (4x and 5x opcodes). To describe these in the opcode charts, we use: cccc Bits 0 - 3 determine a condition code: BITS 0 - 1 - Jump if the TST pin is zero 1 - 2 - Jump if carry is set 2 - 4 - Jump if accumulator is 0 3 - 8 - If set, invert the jump condition The following 16 options result: IACT - Invert, Accumulator, Carry, TST pin 0000 - Never jump 0001 - Jump if the TST pin is zero 0010 - Jump if c = 1 0011 - Jump if c = 1 OR TST pin is zero 0100 - Jump if A = 0 0101 - Jump if A = 0 OR TST pin is zero 0110 - Jump if A = 0 OR c = 1 0111 - Jump if A = 0 OR c = 1 OR TST pin is zero 1000 - ALWAYS jump 1001 - Jump if TST pin is not zero 1010 - Jump if c = 0 1011 - Jump if c = 0 AND TST pin is not zero 1100 - Jump if A != 0 1101 - Jump if A != 0 AND TST pin is not zero 1110 - Jump if A != 0 AND c = 0 1111 - Jump if A != 0 AND c = 0 AND TST pin is not zero rrr - Bits 1 - 3 which determine which pair of general registers to use: 000 - R0R1 001 - R2R3 010 - R4R5 011 - R6R7 100 - R8R9 101 - RARB 110 - RCRD 111 - RERF rrrr - Bits 0 - 3 which determine which general register to use aaaa - Bits 0 - 3 become bits 8 to 11 in a 12bit address dddd - Bits 0 - 3 are the 4bit immediate value If an opcode takes a second byte for data (8bit addressing, 12bit addressing and 8bit immediate), that byte follows the opcode byte. ___________________________________________________________________________________________________ 4.2 Mnemonic Listing Format Each opcode has a C-style psuedo code snip, and a textual description of the opcodes. VERY IMPORTANT: If an operand or register value is used, it is assumed that it has the same bit depth as the value would on the real CPU being emulated. This means that a 4bit value that is 0x0F, when incremented will become 0x00 NOT 0x10 which is impossible for a 4bit value! Unless a code section says "Code: [Full Version]", we are assuming that: Before starting the code: The effective address(es) are already calculated PC incremented as necessary If there is an operand read in, it will be in the operand variable If two operands are read in, the first (destination) will be operand1 and the second (source) will be operand2 After the code: If any data is written out (eg, operand1), it will be output/stored/etc. Value/Variable Definitions: A Refers to the Accumulator c Refers to the carry flag. This value can only be 0 (false) or 1 (true) If any non-zero value is assigned to it, it becomes 1 PC[x] Refers to the Program Counter (12bit). The x will usually be S, meaning the current PC based off of the Stack register Rx Refers to a general register (x may be replaced with 0 to F) S Refers to the 2bit Stack register Xx Refers to the four RAM address registers X0 to X3. Specials: CPU The CPU type. This will be one of the CPU types above For example, if we're on a 4040, CPU will hold 4040. We can test for it with (CPU == 4040) This is to show differences in how different CPUs handle opcodes highbit Holds the value of the highest bit of the register's current size operand Holds the current operand. If operand is modified, the opcode updates it in memory (or the register it applies to, if applicable) operand1 The first operand when multiple operands exist in an opcode operand2 The second operand when multiple operands exist in an opcode result The result before it is stored anywhere tempS8 A temporary signed 8bit value value May hold the value from the operand when we may want to modify the operand without storing it back where it came from. This is also used to hold an immediate value ___________________________________________________________________________________________________ 4.3 Alphabetic Mnemonic Listing and Full Descriptions --------------------------------------------------------------------------------------------------- ADD ADD general register to accumulator with carry Description: .......................................................................... Adds the specified general register, the accumulator and carry, storing the result in the accumulator and setting carry if the result was greater than 0x0F (15), otherwise clearing it. Flags: ................................................................................ c * Carry is set if the result was greater than 0x0F (15), otherwise it is clear Code: ................................................................................. result = operand + A + c; A = result & 0x0F; c = result > 0x0F; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 1000rrrr ADD reg4 * 8 8 1 --------------------------------------------------------------------------------------------------- ADM ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11101011 ADM * 8 8 1 --------------------------------------------------------------------------------------------------- BBL Branch Back and Load data into the accumulator Description: .......................................................................... Decrements the stack pointer (the one controlling which program counter is in use) and sets the accumulator to the immediate value. Flags: ................................................................................ c - Code: ................................................................................. A = value; S--; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 1100dddd BBL imm4 ? 8 8 1 --------------------------------------------------------------------------------------------------- CLB ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11110000 CLB 0 8 8 1 --------------------------------------------------------------------------------------------------- CLC ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11110001 CLC 0 8 8 1 --------------------------------------------------------------------------------------------------- CMA ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11110100 CMA 8 8 1 --------------------------------------------------------------------------------------------------- CMC ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11110011 CMC * 8 8 1 --------------------------------------------------------------------------------------------------- DAA ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11111011 DAA 8 8 1 --------------------------------------------------------------------------------------------------- DAC ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11111000 DAC 8 8 1 --------------------------------------------------------------------------------------------------- DCL ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11111101 DCL 8 8 1 --------------------------------------------------------------------------------------------------- FIM Fetch IMmediate from rom Description: .......................................................................... Loads the specified general register pair with the 8bit immediate value. Flags: ................................................................................ c - Code: ................................................................................. operand1 = operand2; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 0010rrr0 FIM reg8, imm8 ? 16 16 2 --------------------------------------------------------------------------------------------------- FIN Fetch INdirect from rom Description: .......................................................................... The 8bit content of the R0R1 register pair is used as an address to the current page of memory (based on PC where the instruction occurs). That byte of memory is then read and loaded into the specified register pair. NOTE: It seems odd to me that this opcode uses the PC value BEFORE the instruction (ie, the PC of the opcode itself) when all 2byte opcodes that use the same page as PC state that it is based on the PC value AFTER the instruction. However, since this opcode also takes two full CPU states like most 2byte opcodes, perhaps PC is decremented before addressing begins. Flags: ................................................................................ c - Code: [Full Version] .................................................................. operand = GetByte((PC[S] & ~0xFF) + (R0 << 4) + R1); PC[S]++; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 0011rrr0 FIN reg8 - 16 16 1 --------------------------------------------------------------------------------------------------- IAC ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11110010 IAC 8 8 1 --------------------------------------------------------------------------------------------------- INC INCrement general register Description: .......................................................................... Increments the specified general register. Flags: ................................................................................ c - Code: ................................................................................. operand++; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 0110rrrr INC reg4 ? 8 8 1 --------------------------------------------------------------------------------------------------- ISZ Increment general register, Skip if Zero Description: .......................................................................... Increments the specified general register. If the result is non-zero, program control is transferred to the address specified in the current page. Note that the upper 4 bits of the PC value used is based AFTER adding 2 to PC (ie, after the instruction) instead of using the upper 4 bits of the PC value. * Opinion: This appears to be the predecessor of the LOOP opcode present in the x86 processors. Most other processors don't have an equivalent of this, so it seems kinda cool that the very first microprocessor had such a thing already in existence. Go Intel! Flags: ................................................................................ c - Code: ................................................................................. operand1--; if (operand1) { PC[S] &= ~0xFF; PC[S] = operand2; } Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 0111rrrr ISZ reg4, addr8 ? 16 16 2 --------------------------------------------------------------------------------------------------- JCN Jump CoNditional Description: .......................................................................... If the specified condition is set, then the lower 8bits of PC are set to the 8bit address specified. See the cccc list above for the available conditions. Note that the upper 4 bits of the PC value used is based AFTER adding 2 to PC (ie, after the instruction) instead of using the upper 4 bits of the PC value. Flags: ................................................................................ c - Code: ................................................................................. // operand1 holds the value of the condition // operand2 holds the 8bit address to use // Are we doing an inverted test? if (operand1 & 0x08) { // Default to true condition_is_true = 1; // Test accumulator, if necessary if (operand1 & 0x04 && A == 0) condition_is_true = 0; // Test carry, if necessary if (operand & 0x02 && c) condition_is_true = 0; // Test the TST pin if (operand & 0x01 && TST_Pin_Is_Zero) condition_is_true = 0; // Or is it a normal test? } else { // Default to false condition_is_true = 0; // Test accumulator, if necessary if (operand1 & 0x04 && A == 0) condition_is_true = 1; // Test carry, if necessary if (operand & 0x02 && c) condition_is_true = 1; // Test the TST pin if (operand & 0x01 && TST_Pin_Is_Zero) condition_is_true = 1; } if (condition_is_true) { PC[S] &= ~0xFF; PC[S] += operand2; } Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 0001cccc JCN cond, addr8 - 16 16 2 --------------------------------------------------------------------------------------------------- JIN Jump INdirect Description: .......................................................................... The register pair is used to jump to an 8bit address in the same page of memory (256 bytes). Flags: ................................................................................ c - Code: ................................................................................. // Clear out the lower byte PC[S] &= ~0xFF; // OR in the lower byte PC[S] |= operand; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 0011rrr1 JIN reg8 - 8 8 1 --------------------------------------------------------------------------------------------------- JMS JuMp to Subroutine Description: .......................................................................... The stack register is incremented, then the new program counter is loaded with the full 12bit address specified. Flags: ................................................................................ c - Code: ................................................................................. S++; PC[S] = operand; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 0101aaaa JMS addr12 ? 16 16 2 --------------------------------------------------------------------------------------------------- JUN Jump UNconditional Description: .......................................................................... The program counter is loaded to the full 12bit address specified. Flags: ................................................................................ c - Code: ................................................................................. PC[S] = operand; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 0100aaaa JUN addr12 - 16 16 2 --------------------------------------------------------------------------------------------------- KBP ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11111100 KBP 8 8 1 --------------------------------------------------------------------------------------------------- LD LoaD general register to accumulator Description: .......................................................................... Loads a 4bit general register into the accumulator Flags: ................................................................................ c - Code: ................................................................................. A = operand; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 1010rrrr LD reg4 ? 8 8 1 --------------------------------------------------------------------------------------------------- LDM Load Data to accuMulator * Opinion: Why this wasn't called LDA is beyond me. Description: .......................................................................... Loads the 4bit immediate value into the accumulator. Flags: ................................................................................ c - Code: ................................................................................. A = operand; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 1101dddd LDM imm4 ? 8 8 1 --------------------------------------------------------------------------------------------------- NOP No Operation Description: .......................................................................... This opcode does nothing Flags: ................................................................................ c - Code: ................................................................................. // Nothing Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 00000000 NOP - 8 8 1 --------------------------------------------------------------------------------------------------- RAL ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11110101 RAL * 8 8 1 --------------------------------------------------------------------------------------------------- RAR ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11110110 RAR * 8 8 1 --------------------------------------------------------------------------------------------------- RDx ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11101100 RD0 8 8 1 11101101 RD1 8 8 1 11101110 RD2 8 8 1 11101111 RD3 8 8 1 --------------------------------------------------------------------------------------------------- RDM ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11101001 RDM ? 8 8 1 --------------------------------------------------------------------------------------------------- RDR ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11101010 RDR ? 8 8 1 --------------------------------------------------------------------------------------------------- SBM ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11101000 SBM * 8 8 1 --------------------------------------------------------------------------------------------------- SRC Send Register Control Description: .......................................................................... The 8bit content of the specified register pair is stored in the RAM address registers X2 and X3. ??????? Flags: ................................................................................ c - Code: ................................................................................. X2 = operand >> 4; X3 = operand & 0x0F; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 0010rrr1 SRC reg8 ? 8 8 1 --------------------------------------------------------------------------------------------------- STC ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11111010 STC 1 8 8 1 --------------------------------------------------------------------------------------------------- SUB SUBtract general register from accumulator with borrow Description: .......................................................................... Subtracts the specified general register from the accumulator. If carry is 0 (borrow), we subtract one more. NOTE: [1] has scribbles in it. The printed document shows that we add the inverse of carry, the inverse of the register and the accumulator together, whereas the scribbles show that carry is used directly. In the print, it states: "If a borrow is generated, the carry bit is set to 0, otherwise, it is set to 1." So, let's assume that this part is true. To properly borrow the result on say 4 - 1, we'd need to end up with 2 (4 - 1 and -1 more for the borrow), meaning we subtract 1 if the cart bit is CLEAR. No documentation I have properly clarifies this, so for now I am going to assume that the scribbles are wrong and the 4004 acted like the 6502 processors in that carry is BACKWARDS from other CPUs like the x86. Flags: ................................................................................ c * Carry is clear if a borrow is generated, otherwise it is set. Code: ................................................................................. tempS8 = A - operand; if (!c) tempS8--; c = (tempS8 >= 0) ? 0 : 1; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 1001rrrr SUB reg4 * 8 8 1 --------------------------------------------------------------------------------------------------- TCC ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11110111 TCC 0 8 8 1 --------------------------------------------------------------------------------------------------- TCS ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11111001 TCS 0 8 8 1 --------------------------------------------------------------------------------------------------- WMP ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11100001 WMP ? 8 8 1 --------------------------------------------------------------------------------------------------- WPM ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11100011 WPM ? 8 8 1 --------------------------------------------------------------------------------------------------- WRx ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11100100 WR0 ? 8 8 1 11100101 WR1 ? 8 8 1 11100110 WR2 ? 8 8 1 11100111 WR3 ? 8 8 1 --------------------------------------------------------------------------------------------------- WRM ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11100000 WRM ? 8 8 1 --------------------------------------------------------------------------------------------------- WRR ??? Description: .......................................................................... ??? Flags: ................................................................................ c - Code: ................................................................................. ??? Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 11100010 WRR ? 8 8 1 --------------------------------------------------------------------------------------------------- XCH eXCHange general register and accumulator Description: .......................................................................... Switches the value of the accumulator and the specified register. Flags: ................................................................................ c - Code: ................................................................................. temp = A; A = operand; operand = temp; Opcodes: .............................................................................. Opcode Mnemonic Parameters C 4004 4008 Bytes 1011rrrr XCH reg4 - 8 8 1 *************************************************************************************************** 5 Interrupts The 4004 CPU does not have interrupts, per se. The only outside "interrupt" accepted is a reset. Reset: Requires at least 64 clocks All of RAM set to 0 FF = 0 PC = 0 S = 0 CM-RAM is selected (??? what does this mean) KERBLUH - does anything happen to the registers? [1] hints that they're cleared but it may just be oddly worded The 4040 adds support for an interrupt [KERBLUH - Need more info] *************************************************************************************************** 6 Pins [INCOMPLETE] 4004: From [4] Out: SYNC Generated every 8 clock periods In: CLK1 The first of two non-overlapping clock phases sent to the processor CLK2 The second of two non-overlapping clock phases sent to the processor TST RST Causes a reset if held low for 64 clocks *************************************************************************************************** 7 Quirks and Nuances [INCOMPLETE] *************************************************************************************************** A1 Miscellaneous Notes and Issues *************************************************************************************************** A2 TO DO List Find information on the 4040, if possible Figure out how RAM works on these procs! *************************************************************************************************** A3 Updates List *************************************************************************************************** Sources Information Sources [1] MCS-4 Micro Computer Set, Rev 4 (c) February 1973, Intel * Used to get details on the 4004 processor [2] 4004 Instruction Set http://neil.franklin.ch/Info_Texts/ (c) January 2nd, 2007, Neil Franklin [3] Wikipedia Article: Intel 4004 http://en.wikipedia.org/wiki/Intel_4004 (c) January 3rd, 2007 [4] 4004 Instruction Set and Data (c) ???, unknown [5] Intel 4040 Microprocessor Family http://www.cpu-world.com/CPUs/4040/index.html (c) November 4th, 2006