M68K Processor Data by: Mark Ormston (aka Zolaerla or MeMSO) of NeueTECH Software memso@memso.net Version: 0.1-PREVIEW Date Created: 2007-09-24 Last Modified: 2007-11-06 Please leave this notice in any version of this text file! This document was made for readability in any general ASCII system, with 100 or more characters per line and 2 spaces per tab. I shall endeavor to convert all tabs to spaces before releasing a version of this document, but if I forget, this at least tells you how to correct it. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! NOTICE! Though I attempt to be as accurate as possible, I am limited to what other sources state. Often times these sources disagree with one another and I end up having to pick and choose what sounds "right", even if it may not necessarily be so. I can give no guarantee of any sort that this information is 100% accurate. I just would like to think it is! If there is any information that would make this more complete, please email me above and let me know! Please put "For MeMSO" (capitalize it properly please) in the subject so I know it's not spam (I get up to 200 of those a day!). !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! This document describes in full detail exactly how the M68K family of processors work, including the CPU32, 68881 and 68882. This information was gathered so I could program the CPU cores into my emulator. Anybody that knows much of anything about emulators knows that they need to be very exact to properly emulate the systems they are designed for, and it is this exactness I sought when creating this document. Many sources were used, and I have listed as many as I could in an appendix. A .xls file should come with this file. It contains charts of the opcodes/mnemonics in Opcode and Mnemonic sort order, for reference purposes. I have used this chart extensively myself. This document currently covers the following processors: 68000 68008 68010 CPU32 68020 68030 68040 68060 - not yet 68881 - not yet 68882 - not yet What this document *IS*: o Quite Unabridged o A gathering of information from many, many different sources to consolodate information in just a couple files o Useful for details on the inner workings of these CPUs o A place to find psuedo-code for EVERY opcode (often times not optimized for clarity's sake) o Will give all information necessary to both program and to emulate these processors o System independent. The code and descriptions of the CPUs ignore any hardware they are designed for as much as is humanly possible. What this document *IS NOT*: o A teaching guide for using/programming these processors o A guide for creating computers/systems using these processors (unless you just want the CPU details) o System dependent Hexidecimal values on the 68000 processors is done with a $ at the beginning of the value. $10 is 10 hex (16 decimal), for example. Because these processors use this convention, I am using it throughout the documentation. I personally would prefer to use 0xABCD like C/C++ does, but any other M68K documentation will also use the $ABCD notation. Throughout this document, I may add an indented section with "* Opinion" to show when I am stating my opinion on something. These may be ignored completely but may point out something that you may not otherwise think about. [x] - I use this to denote sources. For example, if I mention something from "Motorola M68000 Family Programmer's Reference Manual", I will simply call it [1]. See Sources at the end of the file for a list of sources. ??? - I put this anywhere where I am making a guess but do not know for certain. These are very frustrating for everyone I'm certain. KERBLUH - This is what I use to tell me that more information is needed. *************************************************************************************************** TABLE OF CONTENTS 1 Description of the M68K line of processors 2 List of processor registers 3 Addressing Modes 4 Building Opcodes 5 Integer Mnemonics/Opcodes List 6 Floating Point Mnemonics/Opcodes List 7 MMU Mnemonics/Opcodes List 8 Data Formats 8.1 Binary Coded Decimal (BCD) - Packed and Unpacked 8.2 Bit Fields 9 Interrupts 10 Pins 11 Quirks and Nuances 11.1 Nuances (Intentional Processor Behavior) 11.2 Quirks/Bugs ___________________________________________________________________________________________________ A1 Miscellaneous Notes and Issues A2 List of computers/game systems that used these processors Probably forever incomplete, but I can try A3 TO DO List A4 Updates List ___________________________________________________________________________________________________ Sources Information Sources ___________________________________________________________________________________________________ In the Spreadsheet: Sheet1 List of all opcodes, sorted by Mnemonic *************************************************************************************************** Descriptions of the 68000 processors [COPIED FROM ELSEWHERE FOR THE MOMENT] A) MC680x0 ------------ The original MC68000 has the following general features: * CISC - Complex Instruction Set Computer architecture. * eight 32 bit general purpose data registers (D0-D7). * eight 32 bit general purpose address registers (A0-A7). (A7 is the stack pointer - user or supervisor) * 32 bit Program Counter - linear 4 gigabyte - no paging or segments. * 16 bit external data bus - needs 16 bit ROM and RAM for system. Can access 8 or 16 bit memory and peripheral devices. * 16 Mbyte linear addressing range (23 bit plus Upper* and Lower* data strobes for an effective 24 bit range), 32 bit with 68020. * 56 Instruction types - over 1000 useful permutations are possible. * memory mapped I/O. (peripheral registers addressed as memory). * 14 addressing modes on a contiguous address space (no segments). * 5 main data types. (bit, byte, BCD, word and long word). * Supervisor and User states. Stack Pointer A7 is set to User (USP) or Supervisor SP (SSP) by a bit in the status register. * Exception processing and 7 levels of interrupts. * Tracing function - each instruction ends in a TRAP to user program. * Asynchronous bus structure. Uses DTACK* from the peripheral chip. * non-multiplexed address and data buses - interfaces with LS-TTL. * Bus Arbitration Control circuitry. * 5 volt NMOS dynamic construction. (the 68HC000 is a CMOS 68000) The 68HC000 is a CMOS version of the NMOS MC68000. The 68EC000 is a CMOS version of the 68000 with a switchable (at reset) 8 or 16 bit data bus. It is not a static device - the minimum clock frequency is 4 Mhz. It is designed for the embedded controller market. Exception processing results from interrupts, TRAP instructions, a bus or address error or a reset. This feature simplifies software development by detecting bugs and errors and helps prevent "run-away" conditions. The Exception Vector table is normally made of 255 32 bit vectors using 1024 bytes of memory starting at location 0. The CPU loads the appropriate vector, containing the 32 bit address of the routine to service the exception, from this table at the occurrence of an exception such as reset, bus or address error, word access to odd memory location, TRAP and others. This table is usually constructed in RAM by the operating system during the initialization period. There are 192 user interrupt vectors reserved. The initial SSP (Supervisor Stack Pointer) and initial PC (for RESET) occupy memory location $0 and $4 which usually maps out to ROM. The CPU can only switch from USER mode to the SUPERVISOR mode via exception processing. The majority of programs are meant to execute in the User Mode. The Supervisor Mode is used by the operating system to access system resources. The processor is in the Supervisor Mode at RESET. A system can operate continuously in the Supervisor Mode. MC68008: The 68008 is a MC68000 with a 8 bit data bus in a 48 pin DIP or a 52 pin PLCC. The RAM, ROM and peripheral chips must have 8 bit data paths. The DIP package address bus is 20 bits (1 mbyte) and the PLCC device has 22 bits (4 mbytes). A0 is present on both these parts. The 68008 is listed as "not recommended for new designs". Other devices such as the MC68HC001, 68EC000 and the 68302 have a switchable (at reset) 8 or 16 bit data bus. MC68010: The 68010 is a 68000 with the addition of virtual machine and virtual memory capabilities and a "loop mode" which acts like a 3 word instruction cache. This processor is listed as "not for new designs". A 68010 will plug into a 68000 socket and work in most systems. Three new registers are added. The Vector Base Register (VBR) determines where in memory the vector table is located which allows for multiple tables to implement the virtual machine and memory functions. The Alternate Function Code Registers (SFC and DFC) allow the Supervisor mode to access user data space or emulate CPU space cycles. The instruction set is essentially the same for the 68000/08/10. The 68010 supports modular programming. The CPU32 processor used in the 68300 series is a 68010 with some 68020 instructions added. MC68020: The MC68020 incorporates 32 bit address and data paths and Dynamic Bus Sizing to "size" peripherals and memory on a cycle-by-cycle basis to 8, 16 or 32 bit lengths using signals supplied by external hardware to the SIZ0-1 pins. The 68020 is software compatible to all earlier 68K members. A co-processor interface is provided in the instruction set. All virtual features of the 68010 are preserved. The multiply and divide instructions use 32 bit operands and branch displacements can be 32 bits. A new data type, the "quad word" is 64 bits and used in the multiply and divide instructions. Over 20 new instructions have been added. A 256 byte instruction cache has been added along with two cache registers (CACR and CAAR). A Master Stack Pointer (MSP) (32 bits) has been added to facilitate Multi-Tasking Operating Systems. MC68030: The MC68030 is essentially an improved 68020. The MC68030 incorporates a paged memory management unit (MMU) and 256 byte instruction and data caches (modified Harvard Architecture). The internal MMU implements most of the functions of the MC68851 MMU. Two 64 bit, three 32 bit and one 16 bit registers have been added for MMU control functions. The improved bus interface supports "burst mode", asynchronous and synchronous memory accesses as well as dynamic bus sizing support. The Burst Mode fills the data and instruction caches with bytes from external memory independently with four accesses in a row. Many functions of the 68030 operate in parallel increasing throughput. The 68030 can switch between synchronous and asynchronous modes "on the fly". The '030 is a device useful for new designs and is available in PGA and surface mount packages up to 50 Mhz. MC68040: The MC68040 adds a Floating Point Unit (FPU), separate memory managers for data and instruction memory and 4 Kbyte data and instruction caches. The '040 has 32 bit data and address busses with synchronous bus cycles and uses a full Harvard architecture. The 68040 (as well as the 68060) does not support dynamic bus sizing as in the '020 and '030. The MC68150 will add this feature to the '040 and '060. A new instruction, MOVE16, has been added which performs 16 byte block transfers using burst read and writes for high speed. The built-in FPU utilizes most of the instructions of the MC68882 FPU. For a no-cost software package that simulates the unimplemented instructions, see 040_fpsp under A) Free Software Available. The MC68040 is used in current high power computer systems. There is a special companion mode on the MC68360 QUICC to replace the CPU32+ with a MC68EC040 to increase performance of the QUICC. The 360/EC040 pair reportedly performs at 22 MIPS @ 25 Mhz. MC68050: There is no known 68050 part. The rumour on the Net is that since people were pairing Intel and Motorola processors by part number - ie 6800/8080, 68000/8086, 68010/80186, 68020/80286, 68030/80386 and so on - Motorola decided to break the pattern and jump from the '040 directly to the '060. I have never seen any information from Motorola to suggest this story is true - it is just rumour. It does make appropriate marketing sense. Signetics once (still?) made a Scc68070 that is similar to the MC68000. The official word from Motorola is that odd numbered parts represent minor changes from the previous chip. Even numbers are for major part changes. Another rumour is that the '050 existed at least on paper but when it was shown to major customers, this prototype did not fit into their strategic plans since it was only an improved '040. In view of this, Motorola decided to skip the '050 and go straight to the '060 which also existed on paper then and better fit into the strategies of major customers. MC68060: This is the latest and most powerful member of the 68K family. The '060 is designed as an upgrade from a '040 with 2.5 to 3.5 times the performance of the 25 mhz '040. It uses Superscalar pipelined architecture which means it can perform more than one instruction at a time. The 68060 allows simultaneous execution of two integer instructions (or 1 integer and 1 float instruction) and one branch during each clock cycle. A branch cache allows most branches to execute in zero cycles. This CPU has some RISC processor features. The chip is all hardwired - there is no microcode in it. It incorporates a JTAG interface to help simplify the debugging process. The on-board caches have been increased to 8 Kbytes each and the '060 has 2.5 million transistors on the single die. The '060 uses various dynamic power management techniques to reduce power consumption. The '060 has a clock speed of 50 Mhz currently with a future model at 66 Mhz and since the '060 is a static device, the clock has no lower limit and can even be stopped. This part operates at a Vcc of 3.3 volts and interfaces to both 3 and 5 volt peripherals. The input pins can swing between 0 and 5 volts and the output pins between 0 and 3.3 volts. It has been available as a sample part for some time now and is probably now entering quantity production. This may be the last member of the 68K family. The '060 does not support dynamic bus sizing except with the addition of the MC68150 chip. The '060 offers 100 MIPS @ 66mhz and 250 million operations per second @ 50 mhz. SPECint = 50 @ 50Mhz. There is a M68060 software package (M68060SP) that supplies software emulation for unimplemented integer instructions, FPU software and other library subroutines. This package is available on the Motorola BBS system and now, AESOP. Apple Computer has announced it will not use the MC68060 in the Macintosh. It has switched to the PowerPC RISC chips. The Motorola 68000 series no longer appears to have a future in the desktop market. The '060 will likely find application in advanced high power embedded controllers. It has a list price of $US 308 probably at quantity. (unverified) Motorola claims it will add peripheral devices to the '060 in the future as it has with its 8 bit parts. This is possible because the '060 is of a modular design. The '060 is available in a 223 PGA package and will fit into a 179 pin 68040 super- socket. The extra '060 pins are in towards the center of the socket. ]The '060 is starting to appear in VMEbus computers from such companies as Motorola, Heurikon, EKF, Synergy (2 '060s!) and others. There are '060 accelerator cards available for the Amiga and a European firm called Escom will have the Amiga A4000T/060 computer on the market in late October. This information courtesy of Rask Lambertson in Denmark. It appears the 68K line will have a long life due to its straight forward architecture, simple bus interface and ease of machine language programming. DEVICE TRANSISTORS DEVICE TRANSISTORS MC68000 68,000 MC68302 320,000 MC68008 70,000 MC68330 235,000 MC68010 84,000 MC68340 350,000 MC68020/EC20 190,000 MC68440 26,000 MC68030 273,000 MC68661 6,000 MC68EC030 251,000 MC68681 9,743 MC68040 1,170,000 MC68881 155,000 MC68EC040 962,000 MC68882 176,000 MC68LC040 813,500 MC68901 9,100 MC68060 2,500,000 MC68230 16,700 MC68322 422,000 PPC601 2,800,000 Alpha AXP 21164 9.3 million PPC603 1,600,000 MIPS R8000 3,400.000 PPC604 3,600,000 PPC620 7,000,000 Pentium 3,300,000 P6 > 6 million IntelDX4 1,600,000 --------------------------------------------------------------------------- | Feature | 68000 | 'EC000 | 68010 | 68020 | 68030 | 68040 | 68060 | --------------------------------------------------------------------------- | Data bus | 16 8/16 16 8/16/32 8/16/32 32 32 | | Addr bus | 23 23 23 32 32 32 32 | | Virtual memory | - - Yes Yes Yes Yes Yes | | Instruct Cache | - - 3 256 256 4096 8192 | | Data Cache | - - - - 256 4096 8192 | | Memory manager | <+ (68451 or 68851) +> 68851 Yes Yes Yes | | FPU interface | - - - 68881 or 68882 Internal FPU | | built-in FPU | - - - - - Yes Yes | | Burst Memory | - - - - Yes Yes Yes | | Bus Cycle type | <++++++++ asynchronous +++++++> both synchronous | | Data Bus Sizing| - - - Yes Yes use 68150 | | Power (watts) | 1.2 .13-.26 .13 1.75 2.6 4 - 6 3.9-4.9| | at frequency of| 8.0 8-16 8 ? ? 25-40 50-66 | --------------------------------------------------------------------------- NOTES: a) 68010, 68008, 68451 are apparently no longer available from Motorola. b) FPU (floating point arithmetic unit) has eight 80 bit registers. c) MC68008 is a MC68000 with a 8 bit external data path and A0 pin. d) MC68882 is an enhanced version of the MC68881. Check the appropriate data sheets for more information and interchangeability. e) The MC68000/10 external address bus consists of pins A1 to A23. A0 is an internal signal. Using this scheme, the processor accesses memory in steps of 16 bits for a maximum total of 8 mwords or 16 mbytes of memory. The external outputs UPPER* and LOWER* data strobes can be used to effect byte transfers. See the 68000 data sheet for more detail. Other 68k series members have a A0 pin. All internal address registers are 32 bit. f) MC68060 has a 256 byte entry branch cache. It is also a 3.3 volt part. g) MC68040V and MC68EC040V are 3.3 volt parts, the rest are 5 volts. h) MC68HC000 is low power version of the 68000 using HCMOS technology. i) MC68HC001 is a HC68000 with either a (at reset) 8 or 16 bit data bus. j) The MC68040V, 68LC040, 68EC040 or 68EC040V do not have a FPU. k) The MC68HC000 is a CMOS (low power) version of the MC68000. l) The MC68EC020 is a low cost '020. It has a 24 bit address bus. m) HCMOS= CMOS combined with HMOS (high density NMOS) B) MC68EC0x0 and MC68LC0x0 ---------------------------- This family is essentially a subset of the MC680x0 product line. It is designed for low cost embedded controller applications. The major differences between the two are listed below. Check the appropriate data sheet for more detailed information. a) MC68EC000 is a MC68000 with selectable 8 or 16 bit data bus and A0. b) MC68EC020 is a MC68020 with a 24 bit address bus rather than 32 bits. c) MC68EC030 is a MC68030 without a paged memory manager (PMMU). d) MC68LC040 is a MC68040 without a built-in math coprocessor (FPU). e) MC68EC040 is a MC68040 without a memory manager or built-in FPU. f) MC68LC060 is a MC68060 without a built-in math coprocessor (FPU) g) MC68EC060 is a MC68060 without a memory manager or built-in FPU. External FPUs (MC68881/2) are not easily attached to 68000/08/10, 68EC040 or 68LC040 processors since the co-processor instructions are not present on these CPUs. *************************************************************************************************** Registers +---------------------+ |General Use Registers| +---------------------+ D0 - D7 Generic use Data Registers. These are used for most data/ mathematical operations. The lower 8 bits are used in byte mode, the lower 16 bits are used in word mode, and all 32 bits are used in longint mode. These registers may also be used as index registers. A0 - A7 These are the Address Registers. They are used for pointers and indexes of all sorts, including the stack pointers. A7 is specifically used as the hardware stack pointer, either the USP (in User mode), or the SSP (In Supervisor mode) PC The Program Counter is the current pointer for the program. Execution takes place where PC points. CCR The lower 5 bits are the most important in the Status Register. The lower byte is refered to as the CCR (Condition Code Register). (See list below in Supervisor Registers) USP User Stack Pointer (A7). SP Stack pointer. This always translates to A7. This is the current stack pointer based on the mode of the processor at the time. If the processor is in User mode, it is the User Stack Pointer (USP). If the processor is in Supervisor mode, it is the Supervisor Stack Pointer (SSP). +--------------------+ |Supervisor Registers| +--------------------+ SR - The remainder of the Status Register is available to supervisor- level programs. The full SR follows: 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 T - S - - I2 I1 I0 - - - X N Z V C T - This describes the current trace mode 0 No Tracing 1 Trace on any instruction S - Supervisor/User State (In Supervisor state if set) I0-I2 - Interrupt Mask Level X - Extend Flag. Usually the same as the carry flag, some instructions specifically use this flag (ABCD for example). N - Negative Flag. Set the same as the MSBit of the destination. Z - Zero Flag. Set if the result is zero, otherwise clear. V - Overflow Flag. This is set when the result cannot fit into it's destination. C - Carry Flag. Set if an operand is truncated, either via an addition or a subtraction. Used for multi-precision values. - - All -s in the list need to remain 0 (clear) SSP/A7' - Supervisor Stack Pointer USP/A7 - User Stack Pointer (Can be specified on it's own...) *************************************************************************************************** Addressing Modes Data Register Direct - The value used is in the specified data register. Syntax Dn Mode Field 000 Register Field Register # Extra Words 0 Address Register Direct - The value used is in the specified address register. Syntax An Mode Field 001 Register Field Register # Extra Words 0 Address Register Indirect - The value used is stored at the memory location pointed to by the specified address register. Syntax (An) Mode Field 010 Register Field Register # Extra Words 0 Address Register Indirect w/ Postincrement - This is essentially the same as Address Register Indirect, except that the address register used is then incremented by the amount of memory used. A byte increments by one, a word by two, and a long by four. NOTE: A stack pointer will automatically be increased by two if a byte is used to keep the stack on a word alignment. Syntax (An)+ Mode Field 011 Register Field Register # Extra Words 0 Address Register Indirect w/ Predecrement - This is essentially the same as Address Register Indirect, except that the address register used is first decremented by the amount of memory used, then the value from that new address is used. A byte decrements by one, a word by two, and a long by four. NOTE: A stack pointer will automatically decrement by two if a byte is used to keep the stack on a word alignment. Syntax -(An) Mode Field 100 Register Field Register # Extra Words 0 Address Register Indirect w/ Displacement - This is essentially the same as Address Register Indirect, except a 16-bit value is added to the address before it is used. The 16-bit value is sign extended to 32-bit, allowing a modifier between -32768 and 32767. Syntax (d16, An) Mode Field 101 Register Field Register # Extra Words 1 - disp16 (Same as imm16) Address Register Indirect w/ Index (8-bit displacement) - This is essentially the same as Address Register Indirect with a sign-extended 8-bit value and an Index register added before reading from memory. The extension word contains information about the Index register, whether it is a word or a long. If a word is used, it will be sign extended to a long. The word's low-order byte is the 8-bit displacement. Syntax d8(An, Xn) Mode Field 110 Register Field Register # Extra Words 1 - Extension Word Program Counter Indirect with Displacement - This mode uses the sum of the program counter and a 16-bit (sign extended) displacement value to read a value from memory. NOTE: READ Only! Syntax (d16, PC) Mode Field 111 Register Field 010 Extra Words 1 - disp16 (Same as imm16) Program Counter Indirect with Index (8-bit displacement) - This is essentially the same as Address Register Indirect with Index (8-bit Disp) except the program counter is used in place of the address register. NOTE: READ Only! Syntax (d8, PC) Mode Field 111 Register Field 011 Extra Words 1 - Extension Word Absolute Short Addressing - This uses a sign extended 16-bit value to point at the data to be used. Syntax disp16 -OR- (disp16).W Mode Field 111 Register Field 000 Extra Words 1 - disp16 (Same as imm16) Absolute Long Addressing - This uses a 32-bit value to point at the data to be used. Syntax disp32 -OR- (disp32).L Mode Field 111 Register Field 001 Extra Words 2 - disp32 (Same as imm32) Immediate Data - This uses the immediate data as the value. NOTE: READ Only! Syntax #imm8 -OR- #imm16 -OR- #imm32 Mode Field 111 Register Field 100 Extra Words 1 - imm8 if 8bit 1 - imm16 if 16bit 2 - imm32 if 32bit *************************************************************************************************** Building Opcodes --------------------------------------------------------------------------------------------------- Conditions +--------+----------------+--------+--------------------------+-------------------+ |Mnemonic| Condition |Encoding| Actual Test | Simplified Test | +--------+----------------+--------+--------------------------+-------------------+ | T* | True | 0000 | 1 | | | F* | False | 0001 | 0 | | | HI | Higher | 0010 | !C & !Z | !(C & Z) | | LS | Lower or Same | 0011 | C | Z | | | CC(HS) | Carry Clear | 0100 | !C | | | CS(LO) | Carry Set | 0101 | C | | | NE | Not Equal | 0110 | !Z | | | EQ | Equal | 0111 | Z | | | VC | Overflow Clear | 1000 | !V | | | VS | Overflow Set | 1001 | V | | | PL | Plus | 1010 | !N | | | MI | Minus | 1011 | N | | | GE |Greater or Equal| 1100 | (N & V) | (!N & !V) | !(N ^ V) | | LT | Less Than | 1101 | (N & !V) | (!N & V) | N ^ V | | GT | Greater Than | 1110 |((N & V) | (!N & !V)) & !Z| (!(N ^ V)) & !Z | | LE | Less or Equal | 1111 |Z | ((N & !V) | (!N & V)) | Z | (N ^ V) | +--------+----------------+--------+--------------------------+-------------------+ * Not usable in the Bcc statements Several conditions are a little confusing in what they actually test for, so here's a break down: HI - Unsigned greater than LS - Unsigned less than or equal CC - Unsigned greater than or equal. Aka HS (Higher or Same) CS - Unsigned less than. Aka LO (LOwer) NE - Also used to test for not zero EQ - Also used to test for zero VC - Tests if the previous operation did not cause a signed value to overflow (ie, change signs inappropriately) VS - Tests if the previous operation did cause a signed value to overflow (ie, change signs inappropriately) PL - Was the signed value positive? Also tests if the high bit was clear. MI - Was the signed value negative? Also tests if the high bit was set. GE - Signed greater than or equal LT - Signed less than GT - Signed greater than LE - Signed less than or equal --------------------------------------------------------------------------------------------------- Opcode Variables The whole M68K processor line stores a lot of values into the opcodes themselves. In the opcode charts, I am using a series of letters to represent what these values are. Since the number of letters must match the number of bits for the chart to line up properly, many of those names are confusing. Below is a list of the values that are used for the opcodes: M - R/M bit: 0 - Data 1 - Address w/Predecrement r - Register or Memory source: 0 - Register to Memory 1 - Memory to Register i - i/r field for a CRe: 0 - Count 1 - Register s - Special Size: 0 - Word 1 - Long SI - Size: 00 - Byte 01 - Word 10 - Long 11 - Used by some statements for Word CRe - Count / Register If Count, then a 0-7, 0 meaning 8 If Register, then Data register # REx/REy - Register number (0-7) for destination/source. REd/REa - Register number (0-7) for Data/Address register. OPM - Signifies the mode for the opcode: Normal (ADD, SUB, etc) Byte Word Long 000 001 010 Dn = Dest. 100 101 110 EA = Dest. Address Register Opcodes (ADDA, SUBA, etc) 011 - Word 111 - Long EAM - Effective Address Mode: RG# = Register number to use EAM EAR Description 000 RG# Dn 001 RG# An (Word and Long only) 010 RG# (An) 011 RG# (An)+ 100 RG# -(An) 101 RG# (d16, An) 110 RG# (d8, An, Xn) 111 000 (mem).w 111 001 (mem).l 111 010 (d16, PC) 111 011 (d8, PC) 111 100 #imm EAR - Effective Address Register See EAM above for usage. DAM - Destination Address Mode (See EAM) SAM - Source Address Mode (See EAM) DRE - Destination Register (See EAR) SRE - Source Register (See EAR) NUM - A 3bit value, 0 - 7, with 0 meaning 8 unless otherwise specified COND - Condition check; See list above VECT - Exception Vector (0-15) VEC - 3bit vector (0-7) (used in BKPT) SPOPM - Special Opmode (used in EXG): 01000 - Both Data Registers 01001 - Both Address Registers 10001 - One Data & One Address register 8bitdisp- 8-bit displacement If 00, use the next word for a 16-bit displacement 8bitvalu- 8-bit Value --------------------------------------------------------------------------------------------------- Extra Words Many instructions contain extra words that hold more data for the instruction than the opcode alone can hold. Some of these are unique to specific instructions (such as CAS/CAS2), and others use a common Extension Word used in most opcodes when necessary. Unlike invalid opcodes, the processors ignore certain bits of extra words and do not throw illegal instruction exceptions if the data is invalid. ___________________________________________________________________________________________________ Extension Word This is an extra word with either a data or an address register, Word or Long size designation, an 8bit immediate or displacement, and on the CPU32 and up, a scale/multiplier for the register used. Since both data and address registers may be used in an extension word, the addressing modes that support it will use Xn instead of Dn or An, with the X meaning "indeX register" or a register designated in the Extended Word. 68000, 68010: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+-----------+---+---+---+---+-------------------------------+ |D/A| Register |W/L| 0 | 0 | 0 | 8-bit Displacement Value | +---+-----------+---+---+---+---+-------------------------------+ CPU32 and up: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+-----------+---+-------+---+-------------------------------+ |D/A| Register |W/L| SCALE | 0 | 8-bit Displacement Value | +---+-----------+---+-------+---+-------------------------------+ D/A 0 - Data Register, 1 - Address Register Register 0 - 7 for D0 - D7 or A0 - A7 W/L 0 - Word, 1 - Long If it is a Word, it will be sign extended to 32bits SCALE On the CPU32 and up, a SCALE value is usable for bits 9 and 10. This is the number of bits the index register is shifted before adding to the effective address: 00 - Xn 01 - Xn * 2 10 - Xn * 4 11 - Xn * 8 disp8 Used in specific instructions ___________________________________________________________________________________________________ Immediate Word(s) This word (or words if 32bit) is used when an immediate value is used as an effective address option. 8bit - aka imm8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+-------------------------------+ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8bit Value | +---+---+---+---+---+---+---+---+-------------------------------+ 16bit - aka imm16 or disp16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---------------------------------------------------------------+ | 16bit Value | +---------------------------------------------------------------+ 32bit - aka imm32 or disp32 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---------------------------------------------------------------+ | High 16 bits | +---------------------------------------------------------------+ | Low 16 bits | +---------------------------------------------------------------+ ___________________________________________________________________________________________________ Bit Field Word 68020 and higher Bit field opcodes use a special kind of extra word which I call the "Bit Field Word", to avoid confusion with the "Extension Word". [2] calls all extra words "Extension Words" and in places calls the extension word mentioned above "The Extension Word". In any case, this word defines how the bit field is to be used. It holds the offset, relative to bit 7 [KERBLUH - how do you determine which byte/bit is finally read???] of the first byte of the operand, as well as the width which specifies the number of bits in the bit field. The offset may be 0 to 31 if an immediate is used, or -2^31 to 2^31 - 1 if a data register is used. The width always is between 1 and 32, with 0 meaning 32. Some bit field operations use a destination or source data register, for loading from or storing to a bitfield. These instructions use the Register field. The rest of the bit field opcodes leave 0s in that field. [KERBLUH - what happens if they don't?] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+-----------+---+-------------------+---+-------------------+ | 0 | Register |Do | Offset |Dw | Width | +---+-----------+---+-------------------+---+-------------------+ Register - Specifies the data register to use if a source/destination data register is used by the instruction (BFEXTS, BFEXTU, BFFFO, BFINS) This contains 0s for other opcodes [KERBLUH - what happens if they aren't?] Do - Data type of the offset: 0 - Offset contains a 5bit immediate for the offset This is a value from 0 to 31 1 - Offset specifies a data register for the offset The full register is used, giving an offset range of -2^31 to 2^31 - 1 The top two bits of Offset are always 0 in this mode [KERBLUH - what happens if they aren't?] Offset - The actual offset data, depending on the value of Do. See Do above for details Dw - Data type of the width: 0 - Width contains a 5bit immediate This is a value from 0 to 31 with 1 to 31 meaning 1 to 31 bits respectively and 0 meaning 32 bits 1 - Width specifies a data register for the width The register value modulo 32 is used (only the low 5 bits), giving a value from 0 to 31 with 1 to 31 meaning 1 to 31 bits respectively and 0 meaning 32 bits. The top two bits of Width are always 0 in this mode [KERBLUH - what happens if they aren't?] Width - The actual width data, depending on the value of Dw. See Dw above for details ___________________________________________________________________________________________________ CHK2/CMP2 Extension Word CHK2/CMP2 uses a modified version of the extension word. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+-----------+---+---+---+---+---+---+---+---+---+---+---+---+ |D/A| Register |Op | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +---+-----------+---+---+---+---+---+---+---+---+---+---+---+---+ D/A 0 - Data Register, 1 - Address Register Register 0 - 7 for D0 - D7 or A0 - A7 Op 0 - CMP2, 1 - CHK2 ___________________________________________________________________________________________________ CAS Word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+-----------+---+---+---+-----------+ | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Du | 0 | 0 | 0 | Dc | +---+---+---+---+---+---+---+-----------+---+---+---+-----------+ Dc - Specifies which data register is compared with the memory operand. If they are not equal, this register also receives the value of the memory operand. Du - Specifies which data register is stored into the memory operand if Dc and the memory operand are equal. ___________________________________________________________________________________________________ CAS2 Words 68020 and higher 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+-----------+---+---+---+-----------+---+---+---+-----------+ |DA1| Rn1 | 0 | 0 | 0 | Du1 | 0 | 0 | 0 | Dc1 | +---+-----------+---+---+---+-----------+---+---+---+-----------+ |DA2| Rn2 | 0 | 0 | 0 | Du2 | 0 | 0 | 0 | Dc2 | +---+-----------+---+---+---+-----------+---+---+---+-----------+ Dc1 - Specifies which data register is compared with the first memory operand. If they are not equal or the second two values compared are not equal, this register also receives the value of the first memory operand. Dc2 - Specifies which data register is compared with the second memory operand. If they are not equal or the first two values compared are not equal, this register also receives the value of the second memory operand. Du1 - Specifies which data register is stored into the first memory operand if Dc1 and the first memory operand are equal as well as Dc2 and the second memory operand are equal. Du2 - Specifies which data register is stored into the second memory operand if Dc1 and the first memory operand are equal as well as Dc2 and the second memory operand are equal. Rn1 - This, along with DA1, specifies which register points to the first memory address to compare with. Rn2 - This, along with DA2, specifies which register points to the second memory address to compare with. DA1 - If this is 1, then Rn1 is an address register. If this is 0, Rn1 is a data register. DA2 - If this is 1, then Rn2 is an address register. If this is 0, Rn2 is a data register. ___________________________________________________________________________________________________ Coprocessor Words KERBLUH - Get details on the coprocessor instruction words (cp*). ___________________________________________________________________________________________________ DIVS,DIVSL,DIVU,DIVUL Extension Word CPU32 and higher 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+-----------+---+---+---+---+---+---+---+---+---+-----------+ | 0 | Dq |U/S|SI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Dr | +---+-----------+---+---+---+---+---+---+---+---+---+-----------+ Dq - Specifies the register to receive the quotient. If this and Dr are the same, then , Dq addressing is used. If SI is 1, then this is the low 32 bits of the 64bit dividend. U/S - 0 - Unsigned divide 1 - Signed divide SI - 0 - 32bit dividend is in Dq 1 - 64bit dividend is in Dr:Dq Dr - Specifies the register to receive the remainder. If this and Dq are the same, then , Dq addressing is used. If SI is 1, then this is the high 32 bits of the 64bit dividend. Note that having SI set to 1 AND having Dr and Dq equal is not natively supported by assemblers and has no practical use since it would use the same 32bit value twice for both the low and high 32 bits of the 64bit value. ___________________________________________________________________________________________________ MOVE16 Extension Word MOVE16 uses a modified version of the extension word. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+-----------+---+---+---+---+---+---+---+---+---+---+---+---+ | 1 | Ay | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +---+-----------+---+---+---+---+---+---+---+---+---+---+---+---+ Register 0 to 7 for A0 to A7, the destination register ___________________________________________________________________________________________________ MOVEM Extension Word For all MOVEM types, EXCEPT MOVEM {reglist}, (An)-: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |A7 |A6 |A5 |A4 |A3 |A2 |A1 |A0 |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ For MOVEM {reglist}, (An)-, the registers are reversed: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ |D0 |D1 |D2 |D3 |D4 |D5 |D6 |D7 |A0 |A1 |A2 |A3 |A4 |A5 |A6 |A7 | +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ___________________________________________________________________________________________________ MULS,MULU Extension Word CPU32 and higher This extension word is essentially identical to the DIVS/DIVU extension word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +---+-----------+---+---+---+---+---+---+---+---+---+-----------+ | 0 | Dl |U/S|SI | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Dh | +---+-----------+---+---+---+---+---+---+---+---+---+-----------+ Dl - Specifies the second multiplicand as well as the register that receives the lower 32 bits of the result. U/S - 0 - Unsigned divide 1 - Signed divide SI - 0 - MUL*.L , Dl (Dh is ignored ???) 1 - MUL*.L , Dh-Dl Dh - Specifies the register that receives the higher 64 bits of the result, if SI is 1. If SI is 1 and this register and Dl are the same, then the result is undefined (KERBLUH, what REALLY happens???) If SI is 0, KERBLUH - What happens if we use Dh??? *************************************************************************************************** Opcodes --------------------------------------------------------------------------------------------------- Assembly Format At the end of certain (most) mnemonics will be a period followed by a letter which signifies the size of the operand to use. This is the list: .B - Byte .W - Word .L - Long Word .S - Short (a signed byte, used for Bcc instructions) Flags Affected - A '-' means no change, a '*' means changed, and a '?' means the value is undefined These may also have 0 or 1 if their value is always set the same Quick Description - For a full description of the opcodes, see the section on Mnemonic Descriptions Cycles are in the 68000timings.txt file. Variables: EA The calculated effective address of the instruction EA1 The effective address of the first operand EA2 The effective address of the second operand highbit The value of the highest bit. In a 16bit value, this is bit 15 (32768) opcode Holds the value of the current opcode secondhighbit The value of the second highest bit. In a 16bit value, this is bit 14 (16384) Special functions: ThrowException Throws the specified exception --------------------------------------------------------------------------------------------------- Opcode List ___________________________________________________________________________________________________ ABCD Add Binary Coded Decimal with extend Description: Adds the two operands and the X flag together using BCD (Binary Coded Decimal), storing the result into the second operand. Note that unlike most operations, the Z flag is *NOT* set if the result is zero. It is only cleared if the result is non-zero. To test for zero, you should set the Z flag before using this instruction. This allows for testing for zero across the full precision of any BCD value. Flags: XNZVC *?*?* c - Set on decimal carry, clear otherwise z - Cleared if the result was non-zero, otherwise unchanged x - Same as c Addressing Modes: Mode BWL Dy, Dx B -(Ay), -(Ax) B Code: result16 = operand1 + operand2 + x; // Was there carry on the low nibble? if ((result16 & 0x0F) > 0x09) result16 += 0x06; // Was there carry on the high nibble? if ((result16 & 0xF0) > 0x90) result16 += 0x60; // Was there carry? x = c = result16 > 0x99; // Keep only the low byte operand2 = result16.U8; // Only set z if operand2 is non-zero if (operand2) z = 1; Opcodes: 1100REx10000MREy ABCD src, dest M - Specifies the addressing mode used: 0 - Dy, Dx 1 - -(Ay), -(Ax) ___________________________________________________________________________________________________ ADD ADD Description: Adds the two values together. Note: The X flag is ignored by this operation. To use multiple-precision addition, use the ADDX instruction. Flags: XNZVC ***** c - Set if carry generated, clear otherwise v - Set if overflow generated, clear otherwise z - Set if the result is zero, clear otherwise n - Set if the high bit of the result is set, clear otherwise x - Same as c Addressing Modes: Mode BWL , Dn BWL All address modes are available for . Immediates as a source may also be used in ADDA, ADDI and ADDQ. Dn, BWL Only memory alterable addressing modes are permitted. Dn may be used with as a source, An may be used in ADDA. The encoding normally used by Dn and An in this version is used by the ADDX instruction, and since you can actually do adds to Dn and An with Dn, there is no need for them to be here. Code: result = operand1 + operand2; x = c = result < operand1; z = !result; n = result & highbit; v = ((operand2 ^ operand1 ^ highbit) & (operand2 ^ result)) & highbit; operand2 = result; Opcodes: 1101REnOPMEAMEAR ADD src, dest OPM - Operation Mode: 000 - ADD.B , Dn 001 - ADD.W , Dn 010 - ADD.L , Dn 011 - ADDA.W , An (see ADDA) 100 - ADD.B Dn, 101 - ADD.W Dn, 110 - ADD.L Dn, 111 - ADDA.L , An (see ADDA) ___________________________________________________________________________________________________ ADDA ADD to Address register Description: Adds the two values together with an address register as the destination. If the operand size is Word, the source is sign extended to 32 bits and that value is added to the destination. Unlike ADD, this instruction does not modify any of the condition flags. Flags: XNZVC ----- Addressing Modes: Mode BWL , An -WL All address modes are available for as a source. For the word operation, the source is sign extended to 32bits before adding to An. Code: If (Opcode_Is_Long) temp32 = operand1; Else temp32 = TypeCast(operand1, S32); operand2 += temp32; Opcodes: 1101REnS11EAMEAR ADDA , An S - Size: 0 - ADDA.W , An (source is sign extended to 32bits before adding to An) 1 - ADDA.L , An ___________________________________________________________________________________________________ ADDI ADD Immediate Description: Adds an immediate value to the destination. Note: The X flag is ignored by this operation. To use multiple-precision addition, use the ADDX instruction which is more limiting on what addressing modes are possible. Flags: XNZVC ***** c - Set if carry generated, clear otherwise v - Set if overflow generated, clear otherwise z - Set if the result is zero, clear otherwise n - Set if the high bit of the result is set, clear otherwise x - Same as c Addressing Modes: Mode BWL #imm, BWL Only Dn and memory alterable addressing modes are permitted. ADDA may be used to add an immediate to an address register. Code: result = operand1 + operand2; x = c = result < operand1; z = !result; n = result & highbit; v = ((operand2 ^ operand1 ^ highbit) & (operand2 ^ result)) & highbit; operand2 = result; Opcodes: 00000110SIEAMEAR ADDI #imm, SI - Size: 00 - Byte Operation 01 - Word Operation 10 - Long Operation 11 - Used by CALLM on the 68020. ___________________________________________________________________________________________________ ADDQ ADD Quick Description: Adds an immediate value of 1 to 8 to the destination. If the destination is an address register, a 32bit add occurs and the condition codes are not modified. Note: The X flag is ignored by this operation. To use multiple-precision addition, use the ADDX instruction which is more limiting on what addressing modes are possible. Flags: If the destination is not an address register: XNZVC ***** c - Set if carry generated, clear otherwise v - Set if overflow generated, clear otherwise z - Set if the result is zero, clear otherwise n - Set if the high bit of the result is set, clear otherwise x - Same as c If the destination is an address register: XNZVC ----- Addressing Modes: Mode BWL #imm, BWL Only Dn, An and memory alterable addressing modes are permitted. When adding to an address register, the entire address register is affected (32bit add) and the condition codes are not modified. Code: // If the destination is NOT an address register: result = operand1 + operand2; x = c = result < operand1; z = !result; n = result & highbit; v = ((operand2 ^ operand1 ^ highbit) & (operand2 ^ result)) & highbit; operand2 = result; // If the destination IS an address register: // This is always 32bit operand2 += operand1; Opcodes: 0101NUM0SIEAMEAR ADDQ #imm, NUM - The 3bit value to add. If this is 0, 8 is added. SI - Size: 00 - Byte Operation 01 - Word Operation 10 - Long Operation 11 - Used by various other mnemonics: DBcc (KERBLUH - List) ___________________________________________________________________________________________________ ADDX ADD eXtended Description: Adds the two values together along with the X flag. This provides a mechanism for greater precision values than the processor natively supports. Note: The Z flag is NOT set to 0 if the result is zero. This allows the programmer to set the Z flag before starting a multi-precision add operation and checking it afterwards to see if the entire value was zero or not. Note: Though the encoding for ADDX appears to overlap with ADD and ADDA, they actually never truly overlap. ADDX sets certain bits so that it uses encodings that in ADD would be invalid addressing modes (Dn or An as a destination) and it's size operation is never 11 so it never overlaps with ADDA. Flags: XNZVC ***** c - Set if carry generated, clear otherwise v - Set if overflow generated, clear otherwise z - Cleared if the result is non-zero, unchanged otherwise n - Set if the high bit of the result is set, clear otherwise x - Same as c Addressing Modes: Mode BWL Dy, Dx BWL -(Ay), -(Ax) BWL Code: If (x) { result = operand1 + operand2 + 1; x = c = result <= operand1; } Else { result = operand1 + operand2; x = c = result < operand1; } If (result) z = result; n = result & highbit; v = ((operand2 ^ operand1 ^ highbit) & (operand2 ^ result)) & highbit; operand2 = result; Opcodes: 1101REx1SI00MREy ADDX src, dest SI - Size: 00 - Byte Operation 01 - Word Operation 10 - Long Operation 11 - Used by ADDA.L M - Specifies the addressing mode used: 0 - Dy, Dx 1 - -(Ay), -(Ax) * Interesting note: The 1SI00MREy position of the opcode would normally be ADD Dy, Dx and ADD Dn, An in ADD's Dn, format. Since both of these operations may be done with alternate encodings (ie, ADD Dn, Dn using ADD's , Dn format, and ADDA Dn, An), these encodings are instead used for ADDX. In some respects, ADDX Dy, Dx is encoded how the ADD Dy, Dx would have been, so it just adds the X part of the equation. ADDX -(Ay), -(Ax) takes the place of ADD Dn, An. ___________________________________________________________________________________________________ AND logical AND Description: Performs a bitwise AND of the source operand with the destination operand, storing the result in the destination operand. Flags: XNZVC -**00 z - Set if the result is zero, clear otherwise n - Set if the high bit of the result is set, clear otherwise Addressing Modes: Mode BWL , Dn BWL An may not be used as an operand. Dn, BWL Only Dn and memory alterable addressing modes may be used. Code: operand2 &= operand1; z = !operand2; n = operand2 & highbit; Opcodes: 1100REnOPMEAMEAR AND src, dest OPM - Operation Mode: 000 - AND.B , Dn 001 - AND.W , Dn 010 - AND.L , Dn 011 - Used by ??? 100 - AND.B Dn, 101 - AND.W Dn, 110 - AND.L Dn, 111 - Used by ??? ___________________________________________________________________________________________________ ANDI logical AND Immediate Description: Performs a bitwise AND of an immediate value with the destination operand, storing the result in the destination operand. The size of the immediate value matches the operation size. Flags: XNZVC -**00 z - Set if the result is zero, clear otherwise n - Set if the high bit of the result is set, clear otherwise Addressing Modes: Mode BWL #imm, BWL Only Dn and memory alterable addressing modes may be used. What would normally be ANDI.B #imm, #imm becomes ANDI #imm, CCR Code: operand2 &= operand1; z = !operand2; n = operand2 & highbit; Opcodes: 00000010SIEAMEAR ANDI #imm, SI - Size: 00 - Byte 01 - Word 10 - Long 11 - Used by CHK2.W/CMP2.W ___________________________________________________________________________________________________ ANDI to CCR logical AND Immediate to Condition Code Register Description: Performs a bitwise AND of an immediate value with the condition code register, storing the result in the condition codes. Only bits 0 to 4 are affected. Bits 5 to 7 of CCR are always 0. Flags: XNZVC ***** c - Cleared if bit 0 of operand1 was zero, unchanged otherwise v - Cleared if bit 1 of operand1 was zero, unchanged otherwise z - Cleared if bit 2 of operand1 was zero, unchanged otherwise n - Cleared if bit 3 of operand1 was zero, unchanged otherwise x - Cleared if bit 4 of operand1 was zero, unchanged otherwise Addressing Modes: Mode BWL #imm, CCR B-- Code: // Since AND can never set bits, and the top 3 bits are always 0, we don't need to worry about // the top three bits here CCR &= operand1; Opcodes: 0000001000111100 ANDI #imm, CCR ___________________________________________________________________________________________________ ANDI to SR logical AND Immediate to Status Register Supervisor Instruction Description: Performs a bitwise AND of an immediate value with the status register, storing the result in the status register. Only implemented bits are affected, the other bits are always 0 Flags: XNZVC ***** c - Cleared if bit 0 of operand1 was zero, unchanged otherwise v - Cleared if bit 1 of operand1 was zero, unchanged otherwise z - Cleared if bit 2 of operand1 was zero, unchanged otherwise n - Cleared if bit 3 of operand1 was zero, unchanged otherwise x - Cleared if bit 4 of operand1 was zero, unchanged otherwise Addressing Modes: Mode BWL #imm, SR -W- Code: // Since AND can never set bits and all unimplemented bits are 0, we don't need to worry about // what bits are affected! SR &= operand1; Opcodes: 0000001000111100 ANDI #imm, SR ___________________________________________________________________________________________________ ASL Arithmetic Shift Left Description: This instruction is identical in operation to LSL (Logical Shift Left), except the V flag has a meaning in ASL and is always cleared in LSL. Shifts the bits of the destination operand to the left by the specified number of bits. 0s are shifted into the low bits after each shift. The X and C flags are the value of the last high bit shifted out. The single operand version which affects an value only supports a single bit shift. When an immediate is used for a source operand, 1 to 8 bit shifts are possible. When a data register is used for a source operand, only the low 6 bits of the register are used (Dx & 63) for 0 to 63 shifts possible. Flags: XNZVC ***** c - Set according to the last bit shifted out of the operand, clear for a shift count of zero v - Set if the high bit is changed at any time during the operation, clear otherwise z - Set if the result is zero, clear otherwise n - Set if the high bit of the result is set, clear otherwise x - Set according to the last bit shifted out of the operand, unchanged for a shift count of zero Addressing Modes: Mode BWL Dx, Dy BWL #imm, Dy BWL -W- Only memory alterable addressing modes may be used. Code: // Dx, Dy version // NOTE: This code is actually very slow and is shown only to show what the processor actually // does during the bit shift. v = c = 0; // v and c are cleared even if we don't do a shift temp = operand1 & 63; // Only keep the low 6 bits (0 - 63) If (temp) { For (q = 0; q < temp; q++) { x = c = operand2 & highbit; operand2 <<= 1; // If the high bit has changed, set v If (c != operand2 & highbit) v = 1; } } n = operand2 & highbit; z = !operand2; // #imm, Dn version // NOTE: This code is actually very slow and is shown only to show what the processor actually // does during the bit shift. v = 0; // v starts off cleared For (q = 0; q < operand1; q++) { x = c = operand2 & highbit; operand2 <<= 1; // If the high bit has changed, set v If (c != operand2 & highbit) v = 1; } n = operand2 & highbit; z = !operand2; // version x = c = operand & highbit; // x and c are set to the bit to shift out operand <<= 1; n = operand & highbit; // n is set to the high bit of the result v = c ^ n; // v is set if the high bit changes z = !operand; ___________________________________________________________________________________________________ ASR Arithmetic Shift Right Description: Shifts the bits of the destination operand to the right by the specified number of bits. After each shift, the high bit is preserved. The X and C flags are the value of the last bit shifted out. The single operand version which affects an value only supports a single bit shift. When an immediate is used for a source operand, 1 to 8 bit shifts are possible. When a data register is used for a source operand, only the low 6 bits of the register are used (Dx & 63) for 0 to 63 shifts possible. Flags: XNZVC ***0* c - Set according to the last bit shifted out of the operand, clear for a shift count of zero z - Set if the result is zero, clear otherwise n - Set if the high bit of the result is set, clear otherwise x - Set according to the last bit shifted out of the operand, unchanged for a shift count of zero Addressing Modes: Mode BWL Dx, Dy BWL #imm, Dy BWL -W- Only memory alterable addressing modes may be used. Code: // Dx, Dy version // NOTE: This code is actually very slow and is shown only to show what the processor actually // does during the bit shift. v = c = 0; // v and c are cleared even if we don't do a shift temp = operand1 & 63; // Only keep the low 6 bits (0 - 63) If (temp) { For (q = 0; q < temp; q++) { x = c = operand2 & 1; // This assumes an arithmetic shift right, where the high bit is preserved operand2.S >>= 1; } } n = operand2 & highbit; z = !operand2; // #imm, Dn version // NOTE: This code is actually very slow and is shown only to show what the processor actually // does during the bit shift. v = 0; // v is always cleared in ASR For (q = 0; q < operand1; q++) { x = c = operand2 & 1; // This assumes an arithmetic shift right, where the high bit is preserved operand2.S >>= 1; } n = operand2 & highbit; z = !operand2; // version v = 0; // v is always cleared in ASR x = c = operand & 1; // x and c are set to the bit to shift out // This assumes an arithmetic shift right, where the high bit is preserved operand.S >>= 1; n = operand & highbit; // n is set to the high bit of the result z = !operand; ___________________________________________________________________________________________________ Bcc Branch on Condition Code aka BCC Branch if Carry Clear BCS Branch if Carry Set BEQ Branch if EQual BGE Branch if Greater than or Equal BGT Branch if Greater Than BHI Branch if HIgh BHS Branch if High or Same (same as BCC) BLE Branch if Less than or Equal BLO Branch if LOw (same as BCS) BLS Branch if Low or Same BLT Branch if Less Than BMI Branch if Minus BNE Branch if Not Equal BPL Branch if PLus BVC Branch if oVerflow Clear BVS Branch if oVerflow Set Description: If the specified condition is false, nothing happens and program execution continues. If the specified condition is true, program execution moves to a new location. The initial position of the calculation is PC of the opcode + 2. Then a signed offset is added to the branch, based on the 8bit displacement in the opcode. If the 8bit offset is $00, then a 16bit value is read in after the opcode (which means a branch to the instruction immediately after the branch instruction requires a 16bit value which then would be $02 since the 16bit value occupies two bytes that need to be bypassed). If the 8bit offset is $FF and the CPU is a 68020 or higher (CPU32 excluded), then a 32bit value is read in after the opcode. This gives the 8bit version a range of -127 to -2 (-1 if CPU32 or earlier) and 1 to 126 from 2 bytes after the opcode. The 16bit version is used for a range of -32768 to -128, 0, and 1 to 32767, though technically it could be coded for anywhere in the range of -32768 to 32767. On computers that support 32bit, this gives access to the full 32bit memory range. Flags: XNZVC ----- Addressing Modes: Mode BWL